1. Field of the Invention
This invention relates to a semiconductor memory device, especially relates to a word line drive scheme which is able to achieve a high-speed performance thereof.
2. Description of Related Art
A NAND-type flash memory is known as one of electrically rewritable and non-volatile semiconductor memory devices (EEPROMs). FIG. 20 shows a schematic sectional view of a NAND cell unit, i.e., a basic unit of the NAND-type flash memory. The NAND cell unit is formed of plural memory cells MC0–MC31 connected in series and two select transistors TR1 and TR2. One of the select transistors, TR1, is coupled to a bit line BL, and the other, TR2, to a source line CELSRC disposed common to a memory cell array.
One memory cell has N-type diffusion layers 32 serving as source/drain layers and a stacked gate structure with a floating gate 33 and a control gate 24 stacked thereabove. The control gate 34 is elongated as a word line common to plural memory cells arranged in the direction perpendicular to the section of FIG. 20. This memory cell stores a threshold voltage state defined by the amount of charge in the floating gate as one-bit data or two-bit data in a non-volatile manner. The cell data is rewritable by use of erase and write operations.
FIG. 20 shows a voltage application state at a data write time. Write voltage Vpgm (about 20V) is applied to a selected word line WLi, and write pass voltage Vpass (about 10V) is applied to the remaining unselected (or non-selected) word lines. The select transistors TR1 and TR2 are normal transistors without floating gate. Applied to the select transistor TR1 disposed at the bit line BL side is a voltage equal to or less than a power supply voltage Vdd, and applied to the select transistor TR2 disposed at the source line CELSRC side is 0V. The above-described voltage application state is disclosed, for example, in Published Unexamined Japanese Patent Application No. 2003-208793.
Write data will be applied to the bit lines BL. In detail, 0V and Vdd are applied to the corresponding bit lines in accordance with write data “0” and “1”, respectively. In case of “0” data writing, 0V applied to the bit line BL is transferred to the channel of the selected memory cell MCi, and a voltage of about 20V is applied between the word line WLi and the channel. Therefore, electrons are injected into the floating gate FGi by FN tunneling, thereby resulting in that the threshold voltage of the selected memory cell MCi is shifted to the positive direction. By contrast, in case of “1” data writing (i.e., write inhibition), the select transistor TR1 is cut off when Vdd−Vt (where, Vt is a threshold voltage of the select transistor) is transferred to the channel. Therefore, when the write voltage Vpgm is applied to the selected word line, the floating channel is boosted in potential by capacitive coupling. As a result, FN tunneling current is not carried in the selected memory cell MCi, and the threshold voltage thereof is not varied.
The write voltage pulse application operation will be repeated plural times with a write verify operation for verifying a write state at each cycle in a practical data write sequence. It is required of the NAND-type flash memory to control the “0” write cell's threshold as to be in a voltage region with an upper limit of a certain value lower than a read pass voltage Vread. For this purpose, having confirmed by a write verify operation after write pulse application that a selected memory cell's threshold is over a targeted threshold, the selected memory cell is exchanged hereinafter from a “0” write mode to a “1” write mode in the successive write sequence. That is, the write sequence will be controlled as to continue the write operation only for “0” write memory cells, threshold voltages of which have not yet reached the targeted threshold voltage.
Since data write of the NAND-type flash memory is performed by use of FN tunneling current, it is possible to simultaneously write in a range of a page length with 512-Byte, 2k-Byte or the like. Therefore, the NAND flash memory has a feature that not only it is easy to achieve a memory system with a large capacity, but also data write is done at a substantially great rate. For example, one of the specifications in practical NAND-type flash memories is defined as follows: logical page length is 2k-Byte; and write rate is about 10MB/sec in case of two-value data storing and about 3MB/sec in case of four-value data storing.
Although it is required of a NAND-type flash memory to have an increased capacity and an improved write rate further in future, there is a problem to be solved that a word line has a large CR delay. If the design rule is shrunk in accordance with memory capacity increasing, there is a possibility that the word line becomes to have a CR delay larger than the former one, rather than it is decreased. It is desirable to decrease the word line resistance and/or the wiring capacitance by process improvement, but it is not easy.
For the purpose of high-rate data write, it may be taken some measures on circuitry such as: to shorten the clock cycle of an internal sequencer, which is used for sequence-controlling data write or erase, in correspondence with the chip ability; and to shorten the pulse width in each write pulse application operation. However, with respect to shortening the write pulse width, if over-shortening it, the net time of the write pulse application is decreased, thereby resulting in that the write voltage must be increased. Further, in case the word line delay is large, the write voltage variation on the word line becomes large as dependent on the position of the word line, thereby causing the write rate to be greatly varied as dependent on the position of the word line. Even if the write pulse application time is shortened, this not always leads to improvement of the write performance because of that not only the write voltage becomes high on the average, but also numerous write pulse application operations and write-verify operations are required.